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1 ltc4210-1/ltc4210-2 421012f applicatio s u descriptio u features typical applicatio u the ltc ? 4210 is a 6-pin sot-23 hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. an internal high side switch driver controls the gate of an external n-channel mosfet for a supply voltage ranging from 2.7v to 16.5v. the ltc4210 provides the initial timing cycle and allows the gate to be ramped up at an adjustable rate. the ltc4210 features a fast current limit loop providing active current limiting together with a circuit breaker timer. the signal at the on pin turns the part on and off and is also used for the reset function. this part is available in two options: the ltc4210-1 for automatic retry on overcurrent fault and the ltc4210-2 for latch off on an overcurrent fault. n allows safe board insertion and removal from a live backplane n adjustable analog current limit with circuit breaker n fast response limits peak fault current n automatic retry or latch off on current fault n adjustable supply voltage power-up rate n high side drive for external mosfet switch n controls supply voltages from 2.7v to 16.5v n undervoltage lockout n adjustable overvoltage protection n low profile (1mm) sot-23 (thinsot tm ) package n hot board insertion n electronic circuit breaker n industrial high side switch/circuit breaker hot swap controller in 6-lead sot-23 package , ltc and lt are registered trademarks of linear technology corporation. single channel 5v hot swap controller thinsot and hot swap are trademarks of linear technology corporation. power-up sequence + v cc sense ltc4210 470 f c load v out 5v 4a gnd 4210 ta01 r c 100 gate gnd timer on short long v in 5v gnd long z1: isma10a or smaj10a r on2 10k r on1 20k r x 10 r sense 0.01 pcb edge connector (male) q1 si4410dy z1 optional r g 100 c timer 0.22 f c x 0.1 f c c 0.01 f backplane connector (female) 4210 ta02 10ms/div i out (0.5a/div) v out (5v/div) v on (2v/div) v timer (1v/div) c load = 470 f
2 ltc4210-1/ltc4210-2 421012f (note 1) supply voltage (v cc ) ............................................... 17v input voltage (sense, timer) .. C 0.3v to (v cc + 0.3v) input voltage (on) ..................................... C0.3v to 17v output voltage (gate) ........ internally limited (note 3) operating temperature range ltc4210-1c/ltc4210-2c ....................... 0 c to 70 c ltc4210-1i/ltc4210-2i .................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w order part number LTC4210-1CS6 ltc4210-2cs6 ltc4210-1is6 ltc4210-2is6 t jmax = 125 c, q ja = 230 c/ w timer 1 gnd 2 on 3 6 v cc 5 sense 4 gate top view s6 package 6-lead plastic tsot-23 s6 part marking ltyw ltyx ltf5 ltf6 consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units v cc supply voltage l 2.7 16.5 v i cc v cc supply current l 0.65 3.5 ma v lkor v cc undervoltage lockout release v cc rising l 2.2 2.5 2.65 v v lkohyst v cc undervoltage lockout hysteresis 100 mv i inon on pin input current l C10 0 10 m a i insense sense pin input current v sense = v cc l C10 5 10 m a v cb circuit breaker trip voltage v cb = (v cc C v sense ) l 44 50 56 mv i gateup gate pin pull-up current v gate = 0v l C5 C10 C15 m a i gatedn gate pin pull-down current v timer = 1.5v, v gate = 3v or 25 ma v on = 0v, v gate = 3v or v cc C v sense = 100mv, v gate = 3v d v gate external n-channel gate drive v gate C v cc , v cc = 2.7v l 4.0 6.5 8 v v gate C v cc , v cc = 3v l 4.5 7.5 10 v v gate C v cc , v cc = 3.3v l 5.0 8.5 12 v v gate C v cc , v cc = 5v l 10 12 16 v v gate C v cc , v cc = 12v l 9.0 12 16 v v gate C v cc , v cc = 15v l 6.0 11 18 v i timerup timer pin pull-up current initial cycle, v timer = 1v l C2 C5 C8.5 m a during current fault condition, v timer = 1v l C25 C60 C100 m a i timerdn timer pin pull-down current after current fault disappears, v timer = 1v l 2 3.5 m a under normal conditions, v timer = 1v 100 m a v timer timer pin threshold high threshold, timer rising l 1.22 1.3 1.38 v low threshold, timer falling l 0.15 0.2 0.25 v v tmrhyst timer low threshold hysteresis 100 mv v on on pin threshold on threshold, on rising l 1.22 1.3 1.38 v v onhyst on pin threshold hysteresis 80 mv the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, unless otherwise noted. (note 2) electrical characteristics
3 ltc4210-1/ltc4210-2 421012f ?5 supply current (ma) 150 ?5 ?0 0 25 50 75 100 125 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 temperature ( c) ?5 undervoltage lockout threshold (v) 150 ?5 ?0 0 25 50 75 100 125 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 temperature ( c) ?5 v gate (v) 150 ?5 ?0 0 25 50 75 100 125 40 35 30 25 20 15 10 5 0 temperature ( c) 4210 g01 4210 g02 4210 g03 4210 g04 4210 g05 4210 g06 supply voltage (v) 0 supply current (ma) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 16 4 2 6 10 14 18 8 12 20 t a = 25 c supply voltage (v) 0 v gate (v) 40 35 30 25 20 15 10 5 0 16 4 2 6 10 14 18 8 12 20 t a = 25 c supply voltage (v) 0 i gateup ( a) ?.0 ?.5 ?.0 ?.5 ?0.0 ?0.5 ?1.0 ?1.5 ?2.0 16 4 2 6 10 14 18 8 12 20 t a = 25 c v cc = 15v v cc rising v cc falling v cc = 12v v cc = 5v v cc = 3v v cc = 15v v cc = 12v v cc = 5v v cc = 3v symbol parameter conditions min typ max units t off(tmrhigh) turn-off time (timer rise to gate fall) v timer = 0v to 2v step, v cc = v on = 5v 1 m s t off(onlow) turn-off time (on fall to gate fall) v on = 5v to 0v step, v cc = 5v 30 m s t off(vcclow) turn-off time (v cc fall to ic reset) v cc = 5v to 2v step, v on = 5v 30 m s the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, unless otherwise noted. (note 2) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: an internal zener on the gate pin clamps the charge pump voltage to a typical maximum voltage of 26v. external overdrive of the gate pin beyond the internal zener voltage may damage the device. without a limiting resistor, the gate capacitance must be <0.15 m f at maximum v cc . if a lower gate pin clamp voltage is desired, an external zener diode may be used. typical perfor a ce characteristics uw supply current vs supply voltage supply current vs temperature undervoltage lockout threshold vs temperature v gate vs supply voltage v gate vs temperature i gateup vs supply voltage
4 ltc4210-1/ltc4210-2 421012f ?5 i gateup ( a) 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g07 4210 g08 4210 g09 4210 g10 4210 g11 4210 g12 4210 g13 4210 g14 4210 g15 supply voltage (v) 0 ? v gate (v) 18 16 14 12 10 8 6 4 2 ? v gate (v) 18 16 14 12 10 8 6 4 2 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 16 4 2 6 10 14 18 8 12 20 t a = 25 c i timerup ( a) 0 ? ? ? ? ? ? ? ? ? ?0 v cc = 15v v cc = 15v v cc = 12v v cc = 5v v cc = 3v v cc = 3v v cc = 5v v cc = 12v supply voltage (v) 0 i timerup ( a) 0 ? ? ? ? ? ? ? ? ? ?0 16 4 2 6 10 14 18 8 12 20 t a = 25 c supply voltage (v) 0 i timerdn ( a) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 16 4 2 6 10 14 18 8 12 20 t a = 25 c supply voltage (v) 0 i timerup ( a) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 i timerup ( a) 16 4 2 6 10 14 18 8 12 20 t a = 25 c i timerdn ( a) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 v cc = 5v v cc = 5v v cc = 5v 8.0 8.5 9.0 9.5 ?0.0 ?0.5 ?1.0 ?1.5 ?2.0 typical perfor a ce characteristics uw i timerup (in initial cycle) vs supply voltage i timerup (during circuit breaker delay) vs supply voltage i timerup (during circuit breaker delay) vs temperature i timerdn (in cool-off cycle) vs supply voltage i timerup (in initial cycle) vs temperature i timerdn (in cool-off cycle) vs temperature i gateup vs temperature d v gate vs supply voltage d v gate vs temperature
5 ltc4210-1/ltc4210-2 421012f 4210 g16 supply voltage (v) 0 timer high threshold (v) 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 16 4 2 6 10 14 18 8 12 20 t a = 25 c 4210 g20 supply voltage (v) 0 on pin threshold (v) 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 16 4 2 6 10 14 18 8 12 20 t a = 25 c 4210 g22 supply voltage (v) 016 4 2 6 10 14 18 8 12 20 t a = 25 c 4210 g18 supply voltage (v) 0 timer low threshold (v) 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 timer low threshold (v) 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 16 4 2 6 10 14 18 8 12 20 t a = 25 c ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g17 ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g21 timer high threshold (v) v cc = 5v ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g19 v cc = 5v v cc = 5v high threshold low threshold on pin threshold (v) 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g23 t off,onlow ( s) 80 70 60 50 40 30 20 10 0 t off,onlow ( s) 80 70 60 50 40 30 20 10 0 high threshold low threshold v cc = 15v v cc = 12v v cc = 5v v cc = 3v typical perfor a ce characteristics uw timer low threshold vs temperature on pin threshold vs temperature t off(onlow) vs supply voltage on pin threshold vs supply voltage t off(onlow) vs temperature timer high threshold vs supply voltage timer high threshold vs temperature timer low threshold vs supply voltage
6 ltc4210-1/ltc4210-2 421012f v cb vs supply voltage 4210 g24 supply voltage (v) 0 v cb (mv) 58 56 54 52 50 48 46 44 42 16 4 2 6 10 14 18 8 12 20 v cb (mv) 58 56 54 52 50 48 46 44 42 t a = 25 c ?5 150 ?5 ?0 0 25 50 75 100 125 temperature ( c) 4210 g25 v cc = 5v typical perfor a ce characteristics uw v cb vs temperature uu u pi fu ctio s timer (pin 1): timer input pin. an external capacitor c timer sets a 272.9ms/ m f initial timing delay and a 21.7ms/ m f circuit breaker delay. the gate pin turns off whenever the timer pin is pulled beyond the comp2 threshold, such as for overvoltage detection with an external zener. gnd (pin 2): ground pin. on (pin 3): on input pin. the on pin comparator has a low-to-high threshold of 1.3v with 80mv hysteresis and a glitch filter. when the on pin is low, the ltc4210 is reset. when the on pin goes high, the gate turns on after the initial timing cycle. gate (pin 4): gate output pin. this pin is the high side gate drive of an external n-channel mosfet. an internal charge pump provides a 10 m a pull-up current with zener clamps to v cc and ground. in overload, the error amplifier (ea) controls the external mosfet to maintain a constant load current. an external r-c compensation network should be connected to this pin for current limit loop stability. sense (pin 5): current limit sense input pin. a sense resistor between the v cc and sense pins sets the analog current limit. in overload, the ea controls the external mosfet gate to maintain the sense pin voltage at 50mv below v cc . when the ea is maintaining current limit, the timer circuit breaker mode is activated. the current limit loop/circuit breaker mode can be disabled by connecting the sense pin to the v cc pin. v cc (pin 6): positive supply input pin. the operating supply voltage range is between 2.7v to 16.5v. an under- voltage lockout (uvlo) circuit with a glitch filter resets the ltc4210 when a low supply voltage is detected.
7 ltc4210-1/ltc4210-2 421012f block diagra w + + + + 6 comp1 current limit initial down/normal cool off initial up/latch off 0.2v 60 a 1.3v + comp2 comp3 1.3v on 5 a timer 3 gnd 100 a 2 a glitch filter shutdown m5 gate 4210 bd uvlo v cc sense 50mv ea 5 charge pump 10 a z1 12v z2 26v 4 1 2 logic glitch filter
8 ltc4210-1/ltc4210-2 421012f applicatio s i for atio wu uu hot circuit insertion when circuit boards are inserted into live backplanes, the supply bypass capacitors can draw large transient cur- rents from the backplane power bus as they charge. such transient currents can cause permanent damage to con- nector pins, glitches on the system supply or reset other boards in the system. the ltc4210 is designed to turn a printed circuit boards supply voltage on and off in a controlled manner, allow- ing the circuit board to be safely inserted into or removed from a live backplane. the ltc4210 can reside either on the backplane or on the daughter board for hot circuit insertion applications. overview the ltc4210 is designed to operate over a range of supplies from 2.7v to 16.5v. upon insertion, an undervolt- age lockout circuit determines if sufficient supply voltage is present. when the on pin goes high an initial timing cycle assures that the board is fully seated in the backplane before the mosfet is turned on. a single timer capacitor sets the periods for all of the timer functions. after the initial timing cycle the ltc4210 can either start up in current limit or with a lower load current. once the external mosfet is fully enhanced and the supply has ramped up, the ltc4210 monitors the load current through an exter- nal sense resistor. overcurrent faults are actively limited to 50mv/r sense for a specified circuit breaker timer limit. the ltc4210-1 will automatically retry after a current limit fault while the ltc4210-2 latches off. the ltc4210-1 timer function limits the retry duty cycle to 3.8% for mosfet cooling. undervoltage lockout an internal undervoltage lockout (uvlo) circuit resets the ltc4210 if the v cc supply is too low for normal operation. the uvlo has a low-to-high threshold of 2.5v, a 100mv hysteresis and a high-to-low glitch filter of 30 m s. above 2.5v supply voltage, the ltc4210 will start if the on pin conditions are met. a short supply dip below 2.4v for less than 30 m s is ignored to allow for bus supply transients. on function the on pin is the input to a comparator which has a low- to-high threshold of 1.3v, an 80mv hysteresis and a high- to-low glitch filter of 30 m s. a low input on the on pin resets the ltc4210 timer status and turns off the external mosfet by pulling the gate pin to ground. a low-to-high transition on the on pin starts an initial cycle followed by a start-up cycle. a 10k pull-up resistor connecting the on pin to the supply is recommended. the 10k resistor shunts any potential static charge on the backplane and reduces the overvoltage stress at the on pin during live insertion. alternatively, an external resistor divider at the on pin can be used to program an undervoltage lockout value higher than the internal uvlo circuit. an rc filter can be added at the on pin to increase the delay time at card insertion if the internal glitch filter delay is insufficient. gate function during hot insertion of the pcb, an abrupt application of supply voltage charges the external mosfet drain/gate capacitance. this can cause an unwanted gate voltage spike. an internal proprietary circuit holds gate low before the internal circuitry wakes up. this reduces the mosfet current surges substantially at insertion. the gate pin is held low in reset mode and during the initial timing cycle. in the start-up cycle the gate pin is pulled up by a 10 m a current source. during an overcurrent fault condition, the error amplifier servoes the gate pin to maintain a constant current to the load until the circuit breaker trips. when the circuit breaker trips, the gate pin shuts down abruptly.
9 ltc4210-1/ltc4210-2 421012f sense resistor current flow to load track width w: 0.03" per amp on 1 oz copper w to v cc to sense 4210 f01 current flow to load figure 1. making pcb connections to the sense resistor applicatio s i for atio wu uu current limit circuit breaker function the ltc4210 features a current limiting circuit breaker instead of a traditional comparator circuit breaker. when there is a sudden load current surge, such as a low impedance fault, the bus supply voltage can drop signifi- cantly to a point where the power to an adjacent card is affected, causing system malfunctions. the ltc4210 fast response error amplifier (ea) instantly limits current by reducing the external mosfet gate pin voltage. this minimizes the bus supply voltage drop and permits power budgeting and fault isolation without affecting neighbor- ing cards. a compensation circuit should be connected to the gate pin for current limit loop stability. sense resistor consideration the nominal fault current limit is determined by a sense resistor connected between v cc and the sense pin as given by equation 1. i v r mv r limit nom cb nom sense nom sense nom () () () () == 50 (1) the power rating of the sense resistor should be rated at the fault current level. table 2 in the appendix lists some common sense resistors. for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4210 v cc and sense pins are strongly recommended. the drawing in figure 1 illustrates the connections between the ltc4210 and the sense resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. calculating current limit for a selected r sense , the nominal load current is given by equation 1. the minimum load current is given by equation 2: i v r mv r limit min cb min sense max sense max () () () () == 44 (2) where rr r sense max sense tol () =+ ? ? ? ? 1 100 the maximum load current is given by equation 3: i v r mv r limit max cb max sense min sense min () () () () == 56 (3) where rr r sense min sense tol () = ? ? ? ? 1 100
10 ltc4210-1/ltc4210-2 421012f parasitic oscillations frequently associated with the power mosfet. in some applications, the user may find that r g helps in short-circuit transient recovery as well. however, too large of an r g value will slow down the turn-off time. the recommended r g range is between 5 w and 500 w . usually, method 2 is preferred when the input supply volt- age is greater than 10v. r g limits the current flow into the gate pins internal zener clamp during transient events. the recommended r c and c c values are the same as method 1. the parasitic compensation capacitor c p is required when 0.2 m f < load capacitance c l < 9 m f, other- wise it is optional. parasitic mosfet oscillation there are two possible parasitic oscillations when the mosfet operates as a source follower when ramping at power-up or during current limiting. the first type of os- cillation occurs at high frequencies, typically above 1mhz. this high frequency oscillation is easily damped with r g as mentioned in method 2. the second type of oscillation occurs at frequencies be- tween 200khz and 800khz due to the load capacitance being between 0.2 m f and 9 m f, the presence of r g and r c resistance, the absence of a drain bypass capacitor, a com- bination of bus wiring inductance and bus supply output impedance. there are several ways to prevent this second type of oscillation. the simplest way is to avoid load ca- pacitance below 10 m f, the second choice is connecting an external c p > 1.5nf. applicatio s i for atio wu uu v cc sense r sense 0.007 q1 si4410dy q1 si4410dy v in 5v *additional details omitted for clarity **use c p if 0.2 f < c l < 9 f, otherwise not required 65 c l 4 r c 100 c c 10nf gate ltc4210* (2a) method 1 v cc sense r sense 0.007 r g 200 c p ** 2.2nf v in 12v v out v out 65 4 r c 100 c c 10nf 4210 f02 gate ltc4210* (2b) method 2 + c l + figure 2. frequency compensation if a 7m w sense resistor with 1% tolerance is used for current limiting, the nominal current limit is 7.14a. from equations 2 and 3, i limit(min) = 6.22a and i limit(max) = 8.08a. for proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. the sense resistor power rating must exceed v cb(max) 2 /r sense(min) . frequency compensation a compensation circuit should be connected to the gate pin for current limit loop stability. method 1 the simplest frequency compensation network consists of r c and c c (figure 2a). the total gate capacitance is: c gate = c iss + c c (4) generally, the compensation value in figure 2a is suffi- cient for a pair of input wires less than a foot in length. applications with longer input wires may require the r c or c c value to be increased for better fault transient perfor- mance. for a pair of three foot input wires, users can start with c c = 47nf and r c = 100 w . despite the wire length, the general rule for ac stability required is c c 3 8nf and r c 1k w . method 2 the compensation network in figure 2b is similar to the circuitry used in method 1 but with an additional gate re- sistor r g . the r g resistor helps to minimize high frequency
11 ltc4210-1/ltc4210-2 421012f whichever method of compensation is used, board level short-circuit testing is highly recommended as board layout can affect transient performance. beside frequency compensation, the total gate capacitance c gate also determines the gate start-up as in equation 6. the c gate should be kept below 0.15 m f at high supply operation as the capacitive energy ( 0.5 ? c gate ? v gate 2 ) is discharged by the ltc4210 internal pull-down transistor. this pre- vents the internal pull-down transistor from overheating when the gate turns off and/or is servoing during current limiting. timer function the timer pin handles several key functions with an external capacitor, c timer . there are two comparator thresholds: comp1 (0.2v) and comp2 (1.3v). the four timing current sources are: 5 m a pull-up 60 m a pull-up 2 m a pull-down 100 m a pull-down the 100 m a is a nonideal current source approximating a 7k resistor below 0.4v. initial timing cycle when the card is being inserted into the bus connector, the long pins mate first which brings up the supply v in at time point 1 of figure 3. the ltc4210 is in reset mode as the on pin is low. gate is pulled low and the timer pin is pulled low with a 100 m a source. at time point 2, the short pin makes contact and on is pulled high. at this instant, a start-up check requires that the supply voltage be above uvlo, the on pin be above 1.3v and the timer pin voltage be less than 0.2v. when these three conditions are ful- filled, the initial cycle begins and the timer pin is pulled high with 5 m a. at time point 3, the timer reaches the comp2 threshold and the first portion of the initial cycle ends. the 100 m a current source then pulls down the timer pin until it reaches 0.2v at time point 4. the initial cycle delay (time point 2 to time point 4) is related to c timer by equation: t initial ? 272.9 ? c timer ms/ m f (5) when the initial cycle terminates, a start-up cycle is activated and the gate pin ramps high. the timer pin continues to be pulled down towards ground. applicatio s i for atio wu uu 1 >2.5v comp2 100 a 10 a v in v on v gate reset mode v out v timer 2345 6 7 comp1 4210 f03 5 a initial cycle start-up cycle normal cycle discharge by load v th >1.3v figure 3. normal operating sequence start-up cycle without current limit the gate is released with a 10 m a pull-up at time point 4 of figure 3. at time point 5, gate reaches the external mosfet threshold v th and v out starts to follow the gate ramp up. if the r sense current is below the current limit, the gate ramps at a constant rate of: d d = v t i c gate gate gate (6) where c gate is the total capacitance at the gate pin.
12 ltc4210-1/ltc4210-2 421012f the current through r sense can be divided into two components; i cload due to the total load capacitance (c load ) and i load due to the noncapacitive load elements. the capacitive load typically dominates. for a successful start-up without current limit, i rsense < i limit : i rsense = i cload + i load < i limit ic v t ii rsense load out load limit = d d ? ? ? ? +< (7) due to the voltage follower configuration, the v out ramp rate approximately tracks v gate : d d =? d d = v t i c v t i c out cload load gate gate gate (8) at time point 6, v out is approximately v in but gate ramp- up continues until it reaches a maximum voltage. this maximum voltage is determined either by the charge pump or the internal clamp. start-up cycle with current limit if the duration of the current limit is brief during start-up (figure 4) and it did not last beyond the circuit breaker function time out, the gate behaves the same as in start- up without current limit except for the time interval be- tween time point 5a and time point 5b. the servo amplifier limits i rsense by decreasing the i gate current (<10 m a). ii mv r rsense limit sense == 50 (9) equations 8 and 9 are applicable but with a lower gate and v out ramp rate. gate start-up time the start-up time without current limit is given by: tc vv i tc v i c v i startup gate th in gate startup gate th gate gate in gate = + =+ (10) during current limiting, the second term in equation 10 is partly modified from c gate ? v in /i gate to c load ? v in /i cload . the start-up time is now given by: tc v i c v i c v i c v ii startup gate th gate load in cload gate th gate load in rsense load =+ =+ for successful completion of current limit start-up cycle there must be a net current to charge c load and the current limit duration must be less than t cbdelay . the second term in equation 11 has to fulfill equation 12. c v ii t load in rsense load cbdelay < (12) applicatio s i for atio wu uu v timer v gate v out i rsense v on v in >2.5v 12 345 5a 5b6 7 reset mode initial cycle start-up cycle normal cycle 5 a 100 a comp1 10 a 10 a 60 a 100 a discharge by load regulated at 50mv/r sense v th comp2 2 a <10 a 4210 f04 >1.3v figure 4. operating sequence with current limiting at start-up cycle (11)
13 ltc4210-1/ltc4210-2 421012f circuit breaker timer operation when a current limit fault is encountered at time point a in figure 5, the circuit breaker timing is activated with a 60 m a pull-up. the circuit breaker trips at time point b if the fault is still present and the timer pin voltage reaches the comp2 threshold and the ltc4210 shuts down. for a continuous fault, the circuit breaker delay is: tv c a cbdelay timer = m 13 60 . (13) intermittent overloads may exceed the current limit as in figure 6, but if the duration is sufficiently short, the timer pin may not reach the comp2 threshold and the ltc4210 will not shut down. to handle this situation, the timer discharges with 2 m a whenever (v cc C sense) voltage is below the 50mv limit and the timer voltage is between the comp1 and comp2 thresholds. when the timer voltage falls below the comp1 threshold, the timer pin is discharged with an equivalent 7k resistor (normal mode, 100 m a source) when (v cc C sense) voltage is below the 50mv limit. if the timer pin does not drop below the comp1 threshold, any intermittent overload with an ag- gregate duty cycle of more than 3.8% will eventually trip the circuit breaker. figure 7 shows the circuit breaker response time in seconds normalized to 1 m f. the asym- metric charging and discharging of timer is a fair gauge of mosfet heating. t c sf vf ad a timer (/ ) . m= m m () m 13 1 60 2 (14) when the circuit breaker trips, the gate pin is pulled low. the timer enters latchoff mode with a 5 m a pull-up for the ltc4210-2 (latched-off version), while an autoretry cool- off cycle begins with a 2 m a pull-down for the ltc4210-1 (autoretry version). an autoretry cool-off delay of the ltc4210-1 between comp2 and comp1 thresholds takes: tv c a cooloff timer = m 11 2 . (15) applicatio s i for atio wu uu v timer normal mode fault mode 100 a comp1 circuit breaker trips latched off (5 a pull-up) or retry (2 a pull-down) comp2 ab 60 a 4210 f05 figure 5. a continuous fault timing overload duty cycle, d (%) 10 normalized response time (s/ f) 30 1 4210 f07 0.01 0.1 20 100 90 80 70 60 50 40 0 (s/ f) = t c timer 1.3v ?1 f 60 a ?d ?2 a figure 7. circuit breaker timer response for intermittent overload a1 b1 a2 b2 a3 b3 ~50mv/r sense 60 a circuit breaker trips comp1 4210 f06 comp2 i load v timer v gate 2 a cb fault cb fault cb fault 2 a latched off (5 a pull-up) or retry (2 a pull-down) 60 a 60 a 10 a 10 a figure 6. mulitple intermittent overcurrent conditon
14 ltc4210-1/ltc4210-2 421012f autoretry after current fault (ltc4210-1) figure 8 shows the waveforms of the ltc4210-1 (autoretry version) during a circuit breaker fault. at time point b1, the timer trips the comp2 threshold of 1.3v. the gate pin pulls to ground while timer begins a cool-off cycle with a 2 m a pull-down to the comp1 threshold of 0.2v. at time point c1, the timer pin pulls down with approximately a 7k resistor to ground and a gate start-up cycle is initiated. if the fault persists, the fault autoretry duty cycle is approximately 3.8%. pulling the on pin low for more than 30 m s will stop the autoretry function and put the ltc4210 in reset mode. latch-off after current fault (ltc4210-2) figure 9 shows the waveforms of the ltc4210-2 (latch-off version) during a circuit breaker fault. at time point b, the timer trips the comp2 threshold. the gate pin pulls to ground while the timer pin is latched high by a 5 m a pull- up. the timer pin eventually reaches the soft-clamped voltage (v clamp ) of 2.3v. to clear the latchoff mode, the user can either pull the timer pin to below 0.2v externally or cycle the on pin low for more than 30 m s. applicatio s i for atio wu uu figure 8. automatic retry after overcurrent fault a1 v timer v gate v out i load 4210 f08 b1 c1 a2 b2 comp2 comp1 cb fault cb fault normal mode cool off cycle cool off cycle 60 a 100 a 2 a 2 a 60 a regulating at 50mv/r sense normal mode latched off cycle cb fault 60 a v timer v gate v out i load ab c v clamp comp2 comp1 0v 0v 2410 f09 regulating at 50mv/r sense figure 9. latchoff after overcurrent fault
15 ltc4210-1/ltc4210-2 421012f normal mode/external timer control whenever the timer pin voltage drops below the comp1 threshold, but is not in reset mode, the timer enters normal (100 m a source) mode with an equivalent 7k resis- tive pull-down. table 1 shows the relationship of t initial , t cbdelay , t cooloff vs c timer . if the timer pin is pulled beyond the comp2 threshold, the gate pin is pulled to ground immediately. this allows the timer pin to be used for overvoltage detection, see figure 11. externally forcing the timer pin below the comp1 thresh- old will reset the timer to normal mode. during overvolt- age detection, the timers 100 m a pull-down current will continue to be on if (v cc C sense) voltage is below 50mv. if the (v cc C sense) voltage exceeds 50mv during the overvoltage detection, the timer current will be the same as described for latched-off or autoretry mode. see the section overvoltage detection using timer pin for details of the application. power-off cycle the system can be reset by toggling the on pin low for more than 30 m s as shown at time point 7 of figure 3. the gate pin is pulled to ground. the timer capacitor is also discharged to ground. c load discharges through the load. alternatively, the timer pin can be externally driven above the comp2 threshold to turn off the gate pin. power mosfet selection power mosfets can be classified by r dson at v gs gate drive ratings of 10v, 4.5v, 2.5v and 1.8v. use the typical curves d vgate vs supply voltage and d vgate vs tem- perature to determine whether the gate drive voltage is adequate for the selected mosfet at the operating volt- age. in addition, the selected mosfet should fulfill two v gs criteria: 1. positive v gs absolute maximum rating > ltc4210 maximum d v gate , and 2. negative v gs absolute maximum rating > supply voltage. the gate of the mosfet can discharge faster than v out when shutting down the mosfet with a large c load . if one of the conditions cannot be met, an external zener clamp shown on figure 10a or figure 10b can be used. the selection of r g should be within the allowed ltc4210 package dissipation when discharging v out via the zener clamp. applicatio s i for atio wu uu table 1. t initial , t cbdelay , t cooloff vs c timer c timer ( m f) t initial (ms) t cbdelay (ms) t cooloff (ms) 0.033 9.0 0.7 18.2 0.047 12.8 1 25.9 0.068 18.6 1.5 37.4 0.082 22.4 1.8 45.1 0.1 27.3 2.2 55 0.22 60.0 4.8 121 0.33 90.1 7.2 181.5 0.47 128.3 10.2 258.5 0.68 185.6 14.7 374 0.82 223.8 17.8 451 1 272.9 21.7 550 2.2 600.5 47.7 1210 3.3 900.7 71.5 1815
16 ltc4210-1/ltc4210-2 421012f applicatio s i for atio wu uu d1* q1 gate (10a) (10b) r sense v out r s 200 v cc d2* d1* q1 gate r sense v out r s 200 *user selected voltage clamp (a low bias current zener diode is recommended) 1n4688 (5v) 1n4692 (7v) 1n4695 (9v) 1n4702 (15v) v cc figure 10. gate protection zener clamp figure 11. supply side overvoltage protection + v cc sense ltc4210 6 3 1 2 5 c load 470 f v out 5v 4a gnd 4210 f11 4 r4 100 gate gnd timer on short long v in 5v gnd long r on2 10k r on1 20k r x 10 r sense 0.01 pcb edge connector (male) q1 si4410dy z1 r timer 18 r g 100 c timer 0.22 f c x 0.1 f c c 10nf z2 d1 1n4148 backplane connector (female) r b 10k z1: smaj10a z2: bzx84c6v2
17 ltc4210-1/ltc4210-2 421012f applicatio s i for atio wu uu bypass capacitors, since controlling the surge current to bypass capacitors at plug-in is the primary motivation for the hot swap controller. although wire harness, back- plane and pcb trace inductances are usually small, these can create large spikes when large currents are suddenly drawn, cut-off or limited. this can cause detrimental damage to board components unless measures are taken. abrupt intervention can prevent subsequent damage caused by a catastrophic fault but it does cause a large supply transient. the energy stored in the lead/trace inductance is easily controlled with snubbers and/or transient voltage suppressors. even when ferrite beads are used for electromagnetic interference (emi) control, the low saturating current of ferrite will not pose a major problem if the transient voltage suppressors with ad- equate ratings are used. the transient associated with the gate turn off can be controlled with a snubber and/or transient voltage suppressor. snubbers such as rc net- works are effective especially at low voltage supplies. the choice of rc is usually determined experimentally. the value of the snubber capacitor is usually chosen between 10 to 100 times the mosfet c oss . the value of the snubber resistor is typically between 3 w to 100 w . when the supply exceeds 7v or emi beads exist in the wire harness, a transient voltage suppressor and snubber are recommended to clip off large spikes and reduce the ringing. for supply voltages of 6v or below, a snubber network should be sufficient to protect against transient voltages. in many cases, a simple short-circuit test can be performed to determine the need of the transient voltage suppressor. overvoltage detection using the timer pin figure 11 shows a supply side overvoltage detection circuit. a zener diode, a diode and comp2 threshold sets the overvoltage threshold. resistor r b biases the zener diode voltage. diode d1 blocks forward current in the zener during start-up or output short-circuit. r timer with c timer sets the overload noise filter. a mosfet with a v gs absolute maximum rating of 20v meets the two criteria for all the ltc4210 applications ranges from 2.7v to 16.5v. typically most 10v gate rated mosfets have v gs absolute maximum ratings of 20v or greater, so no external v gs zener clamp is needed. there are 4.5v gate rated mosfets with v gs absolute maximum ratings of 20v. in addition to the mosfet gate drive rating and v gs absolute maximum rating, other criteria such as v bdss , i d(max) , r ds(on) , p d , q ja , t j(max) and maximum safe operating area should also be carefully reviewed. v bdss should exceed the maximum supply voltage inclusive of spikes and ringing. i d(max) should be greater than the current limit, i limit . r ds(on) determines the mosfet v ds which together with v cb yields an error in the v out voltage. at 2.7v supply voltage, the total of v ds + v cb of 0.1v yields 3.7% v out error. the maximum power dissipated in the mosfet is i limit 2 ? r ds(on) and this should be less than the maxi- mum power dissipation, p d allowed in that package. given power dissipation, the mosfet junction tempera- ture, t j can be computed from the operating temperature (t a ) and the mosfet package thermal resistance ( q ja ). the operating t j should be less than the t j(max) specifi- cation. next review the short-circuit condition under maximum supply v in(max) conditions and maximum current limit, i limit(max) during the circuit breaker time-out interval of t cbdelay with the maximum safe operating area of the mosfet. the operation during output short-circuit condi- tions must be well within the manufacturers recom- mended safe operating region with sufficient margin. to ensure a reliable design, fault tests should be evaluated in the laboratory. v in transient protection unlike most circuits, hot swap controllers typically are not allowed the good engineering practice of supply
18 ltc4210-1/ltc4210-2 421012f appe dix u table 2 lists some current sense resistors that can be used with the circuit breaker. table 3 lists some power mosfets that are available. table 4 lists the web sites of several manufacturers. since this information is subject to change, please verify the part numbers with the manufacturer. table 2. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r050 0.05 w 0.5w 1% resistor irc-tt 2a lr120601r025 0.025 w 0.5w 1% resistor irc-tt 2.5a lr120601r020 0.02 w 0.5w 1% resistor irc-tt 3.3a wsl2512r015f 0.015 w 1w 1% resistor vishay-dale 5a lr251201r010f 0.01 w 1.5w 1% resistor irc-tt 10a wsr2r005f 0.005 w 2w 1% resistor vishay-dale table 3. n-channel selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8 on semiconductor r ds(on) = 0.1 w , c iss = 455pf 2 to 5 mmsf5n02hd single n-channel so-8 on semiconductor r ds(on) = 0.025 w , c iss = 1130pf 5 to 10 mtb50n06v single n-channel dd pak on semiconductor r ds(on) = 0.028 w , c iss = 1570pf 10 to 20 mtb75n05hd single n-channel dd pak on semiconductor r ds(on) = 0.0095 w , c iss = 2600pf table 4. manufacturers web sites manufacturer web site temic semiconductor www.temic.com international rectifier www.irf.com on semiconductor www.onsemi.com harris semiconductor www.semi.harris.com irc-tt www.irctt.com vishay-dale www.vishay.com vishay-siliconix www.vishay.com diodes, inc. www.diodes.com
19 ltc4210-1/ltc4210-2 421012f u package descriptio 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 6 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc4210-1/ltc4210-2 421012f lt/tp 0603 1k ? printed in usa ? linear technology corporation 2002 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1421 two channel, hot swap controller operates from 3v to 12v and supports C12v ltc1422 single channel, hot swap controller in so-8 operates from 2.7v to 12v, reset output lt1640al/lt1640ah negative voltage hot swap controller in so-8 operates from C10v to C80v ltc1642 single channel, hot swap controller overvoltage protection to 33v, foldback current limiting ltc1643al/ltc1643ah pci hot swap controller 3.3v, 5v, internal fets for 12v ltc1647 dual channel, hot swap controller operates from 2.7v to 16.5v, separate on pins for sequencing ltc4211 single channel, hot swap controller 2.5v to 16.5v, multifunction current control ltc4230 triple channel, hot swap controller 1.7v to 16.5v, multifunction current control ltc4251 C48v hot swap controller in sot-23 floating supply, three-level current limiting ltc4252 C48v hot swap controller in msop floating supply, power good, three-level current limiting ltc4253 C48v hot swap controller with triple supply sequencing floating supply, three-level current limiting typical applicatio u 12v hot swap application + v cc sense ltc4210 6 3 1 2 5 c load 470 f v out 12v 4a gnd 4210 ta03 4 r c 100 gate gnd timer on short long v in 12v gnd long r on2 10k r on1 62k r x 10 r sense 0.01 pcb edge connector (male) q1 si4410dy z1 r g 200 c timer 0.22 f c x 0.1 f c c 10nf backplane connector (female) z1: smaj12a

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